Precision is very important in the manufacture of semiconductor integrated circuits. Semiconductor integrated circuits commonly include many transistors and active devices that are formed by implanting, depositing and etching certain substances onto the surface of a substrate. The most commonly used substrate for the manufacture of semiconductor integrated circuits is silicon, although those skilled in the art will recognize that many other known and as yet unknown substances can be used for a substrate.
The implanting, depositing and etching process steps are used in the formation of the multi-layer structure that makes up the semiconductor integrated circuit. The technique typically used to implant, deposit and etch employs a series or set of masks that expose or open windows to the surface of the semiconductor integrated circuit in formation. It is not uncommon to require dozens of different masks to implant, deposit and etch the various layers created in the multi-layer structure. Today, these structures can include, for example, three, four or even five layers of metal interconnect in addition to the active devices included in the semiconductor integrated circuit.
As the size, and accordingly the device geometries, of these semiconductor integrated circuits continues to shrink, one problem that emerges is the alignment of the many masks used in the manufacturing process. In the manufacture of sub-micron devices common today, such as 100 nanometer transistors, the alignment of the mask sets used in the manufacturing process can become critical to the operation of the resulting circuits. Improperly aligned or misaligned masks can prevent device operation and thus reduce the yield of the semiconductor integrated circuits manufactured.
One common mask alignment problem is the degree of overlay between different masks in a multiple mask set. Misalignment between successive masks used in the manufacture of the semiconductor integrated circuit can produce an overlay error that may ultimately result in the failure of the circuits to operate properly. Specifically, this overlay error may cause significant differences in the source and drain areas defined for these semiconductor integrated circuits.
Overlay error between the source/drain mask, which is used to define the isolation area between the active areas, and the poly/gate mask thus becomes critical.
In order to reduce the alignment problems created by the use of multiple mask sets, certain self-alignment techniques have been attempted. What is lacking in the art is a totally self-aligned transistor and a method for making the self-aligned transistor where the gate, source, drain and isolation area of the device are all self-aligned using a single mask. What is also lacking is the provision of a mid-gap electrode in such a self-aligned transistor.
In view of the above, a totally self-aligned transistor with tungsten gate and method for making same is provided. According to the device of the invention, the totally self-aligned transistor with tungsten gate includes a substrate layer and at least one silicon trench, the at least one silicon trench defining a plateau region in the substrate layer. An oxide layer is disposed in the at least one silicon trench, and oxide spacers are disposed on a top surface of the plateau region. The oxide spacers define gate, source and drain areas. At least one channel dopant is deposited in the substrate layer on the top surface thereof. Silicide layers are disposed in the source and drain areas between the oxide spacers. A metal layer is deposited in the gate area above the at least one channel dopant and in the source and drain areas above the silicide layers.
According to the method of the invention, a totally self-aligned transistor with tungsten gate is formed by providing an integrated circuit semiconductor structure comprising a substrate layer, a first oxide layer deposited over the substrate, a first nitride layer deposited over the first oxide layer, a second oxide layer deposited over the first nitride layer, and a second nitride layer deposited over the second oxide layer. A photoresist layer is deposited in a predetermined pattern over the integrated circuit semiconductor structure. The second nitride layer is then etched in those areas not covered by the photoresist layer to create at least one nitride island. The integrated circuit semiconductor structure is also etched to create at cast one silicon trench. An oxide layer is deposited in the silicon trench to a level of the first nitride layer. The first nitride layer, the first oxide layer and the at least one nitride island are etched to form gate, source and drain areas, and at least one channel dopant is deposited in the gate area of the substrate layer. A silicide layer is then provided over the source and drain areas, and a metal layer is deposited in the gate, source and drain areas.
As can be seen, the present invention provides a totally self-aligned transistor that reduces or eliminates the overlay error caused by the use of multiple mask sets in the formation of semiconductor integrated circuits. The present invention provides a totally self-aligned transistor where the source, gate and drain of the transistor are all aligned to the isolation area of the device through the use of a single mask to form each of these elements. Deposition of tungsten in the gate area of this device also provides a mid-gap electrode for the totally self-aligned transistor. The present invention thus helps to improve device density and shrink the overall size of semiconductor integrated circuits, as well as add new functionality to such devices.
These and other features and advantages of the invention will become apparent to those skilled in the art upon a review of the following detailed description of the presently preferred embodiments of the invention, taken in conjunction with the appended drawings.